When memory cells are produced in matrix-like arrangements, it is necessary to make contact between each cell and a row and a column line. In order to produce these connections, the cells have to be provided with contacts, which are electrically conductively connected to the lines.
As is described in U.S. Pat. No. 5,482,894 and international application WO 01/09946 A1, when manufacturing DRAM circuits according to the prior art, contacts in the cell array are produced by using a plug/hole mask in a lithographic process. After an exposure and development process, holes are etched in the dielectric between the first metallization layer and the diffusion layer. The etching is in this case carried out selectively for gate encapsulation.
The hole masks which are required for this method are difficult to produce lithographically with the necessary size and accuracy. A further disadvantage occurs as the contact holes become smaller. The subsequent selective etching of the holes as far as the gate encapsulation is more difficult for small structures.
WO 01/09946 A1 describes a method for production of integrated semiconductor components. The necessary contacts are produced first by forming the desired contact as a sacrificial poly-silicon DOT, then by embedding this DOT in BPSG in a subsequent process, and by later removing the sacrificial poly-silicon once again. The contact holes are then filled with a conductive material, thus forming a conductive connection.
In this method, the distance between the structures is very small, owing to the progress in the miniaturization of the memory structures and the use of a checkerboard design. This improves the capability to form resist feet between the resist DOTs that are produced. A disadvantage of the method is that the resist DOTs which are required in the meantime are relatively high, as isolated structures, and can easily fall down.